Semiconductor differential circuit, oscillation apparatus, switching apparatus, amplifying apparatus, mixer apparatus and circuit apparatus using same, and semiconductor differential circuit placement method

ABSTRACT

A semiconductor differential circuit comprising a semiconductor substrate, a first semiconductor device on the semiconductor substrate having a gate electrode for having one of differential signals conveyed thereto and a drain electrode for outputting one of the differential signals controlled by the gate electrode, a second semiconductor device formed on the semiconductor substrate having a gate electrode for having the other of the differential signals conveyed thereto and a drain electrode for outputting the other of the differential signals controlled by the gate electrode, and wherein the drain electrode and drain electrode are placed in the proximity so that, at a predetermined frequency, it is equivalent to the one in which the drain electrode is grounded via a predetermined resistance, and the drain electrode is grounded via the predetermined resistance.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor differential circuit used for a high-frequency circuit of a portable telephone and so on, an oscillation apparatus, an amplifying apparatus and a switching apparatus using the semiconductor differential circuit, and a semiconductor differential circuit placement method.

[0003] 2. Related Art of the Invention

[0004] In conjunction with rapid diffusion of portable telephones, it is becoming increasingly necessary to miniaturize a radio portion thereof. For that reason, it is a trend in recent years to render the radio portion as an IC. To embody the radio portion as an IC, it is necessary to embody as ICs an oscillator and a low noise amplifier which were manufactured with discrete parts and modules in the past.

[0005]FIG. 12 shows an example of a circuit embodied as an IC of an oscillation apparatus in the past. In the circuit shown in FIG. 12, a coil 1002 and a coil 1003 are connected in series, and a power supply 1001 is connected to a connection point of the coil 1002 and coil 1003. A series circuit of the coil 1002 and coil 1003 has a circuit to which switching elements 1006 and 1007 are connected in series via DC blocking capacitors 1004 and 1005 and a circuit to which variable capacity elements 1008 and 1009 are connected in series via DC blocking capacitors 1025 and 1026 connected in parallel thereto. And a negative resistance circuit formed by MOSFETs 1010 and 1020 is connected to a resonant circuit constituted as above so that the circuit as a whole is formed as a differential oscillator. The switching elements 1006 and 1007 are connected with a control voltage terminal 13 so that a frequency band of a calling frequency can be switched by a control voltage applied to the control voltage terminal 13.

[0006]FIG. 13 shows an example of a circuit embodied as an IC of an amplifying apparatus in the past. In the circuit shown in FIG. 13, a coil 1027 and a coil 1028 are connected in series, and a power supply 1029 is connected to the connection point of the coil 1027 and coil 1028. The series circuit of the coil 1027 and coil 1028 has MOSFETs 1030 and 1031 connected thereto so as to form a differential amplifier.

[0007] In the case where the oscillator shown in FIG. 12 is on a silicon substrate (not shown), however, a parasitic capacitance 1023 and a parasitic resistance 1024 are formed between it and the substrate on a drain 1021 side. Therefore, as shown in FIG. 14, the coil 1003 is equivalent to a parallel connection circuit to the series circuit of the parasitic capacitance 1023 and parasitic resistance 1024 as to a high-frequency signal component. Thus, if influenced by the parasitic capacitance 1023 and parasitic resistance 1024, a characteristic of the resonant circuit becomes a blunt one as shown in the broken line which should originally be the one shown in full line as shown in FIG. 15. To be more specific, Q of the resonant circuit deteriorates and C/N deteriorates.

[0008] In the case where an amplifier circuit shown in FIG. 13 is formed on the silicon substrate, the parasitic capacitance 1023 and parasitic resistance 1024 are formed like wise between it and the substrate on the drains 1021 and 1022 side of the MOSFETs. Therefore, a high-frequency signal leaks to the parasitic resistance 1024 via the parasitic capacitance 1023. And a part of the high-frequency signal is lost due to influence of the parasitic resistance. Consequently, a noise characteristic deteriorates due to influence of a parasitic component of a gate, and a distortion characteristic deteriorates due to influence of the parasitic component of a drain.

[0009] In the case where a switching element is formed on the silicon substrate, the parasitic resistance and parasitic capacitance are formed as described above, consequently leading to a loss on turning on the switching element. When used in combination with the above oscillator for instance, in an ON state of the switching element, the resonant circuit is further influenced by the parasitic resistance and parasitic capacitance via the switching element so that the Q-value further becomes blunt and the characteristic deteriorates.

[0010] To solve the above problems, some solutions have been provided. For instance, one solution proposes a constitution in which an oxide film is formed between a semiconductor device and the silicon substrate (refer to Japanese Translation of PCT International Application No. 11-501466 for instance). Thus, it is possible, by forming the oxide film between the semiconductor device and the silicon substrate, to reduce the parasitic capacitance 1023 so as to improve the characteristic deterioration of the oscillator and the low noise amplifier. In reality, however, a manufacturing process had to be changed to implement such a constitution, resulting in a high-cost process.

[0011] Another solution proposes a constitution in which impurity concentration of the silicon substrate is reduced to increase a resistance value of the parasitic resistance 1024 (refer to Japanese Patent Laid-Open No. 8-316420 for instance). The disclosures of Japanese Translation of PCT International Application No. 11-501466 and Japanese Patent Laid-Open No. 8-316420 are incorporated herein by reference in their entireties. FIG. 16 schematically shows the Q-value of the resonant circuit constituting the oscillator shown in FIG. 12 on changing the parasitic resistance 1024. Such a characteristic can be derived from a conductance and susceptance of the resonant circuit as the coils 1002 and 1003 in the circuit shown in FIG. 12 replaced by the circuit shown in FIG. 14. As for the characteristic shown in FIG. 16, the Q-value especially deteriorates in the range in which the parasitic resistance 1024 is 100 to 500 ohms. Therefore, to improve the Q-value of the resonant circuit, the resistance value of the parasitic resistance 1024 should be increased or decreased from the above range. Thus, it is possible, by reducing the impurity concentration of the silicon substrate, to increase the resistance value of the parasitic resistance 1024 so as to improve the characteristic of the oscillating circuit. It is also possible, in the amplifier circuit, to curb the characteristic deterioration by increasing the parasitic resistance. However, this solution also required the manufacturing process to be changed, resulting in a high-cost process.

[0012] A further solution proposes a constitution in which a contact for grounding the silicon substrate is placed as close as possible to the MOSFETs. FIG. 17 is a plan view showing a configuration of such multi-finger type MOSFETs. In the configuration shown in FIG. 17, a source electrode 1032 in a longitudinal shape is placed, a gate electrode 1033 in a longitudinal shape is placed to be adjacent to the source electrode 1032, and a drain electrode 1034 in a longitudinal shape is placed to be adjacent to the gate electrode 1033. And a contactor 1035 connected to a silicon substrate wiring 1036 is placed close to the drain electrode 1034. The silicon substrate wiring 1036 is connected to an earth electrode. It is possible, by such a configuration, to reduce the resistance value of the parasitic resistance 1024 from the drain electrode 1034 to the earth electrode so as to improve the characteristic of the Q-value in the oscillating circuit for the above-mentioned reason. It is also possible, in the amplifier circuit, to curb the characteristic deterioration by reducing the parasitic resistance 1024.

[0013] As for the solution shown in FIG. 17, however, it is necessary to place a large number of contactors 1035 in order to sufficiently reduce a parasitic resistance 1024 in each drain electrode 1034. For instance, if MOSFETs 1010 and 1020 of the oscillating circuit shown in FIG. 12 are implemented on a semiconductor substrate, the placement will be as shown in FIG. 18. Thus, the area for mounting the contactors 1035 and silicon substrate wiring 1036 further becomes necessary so that the entire IC chip becomes large enough to be a factor of increased cost.

[0014] An object of the present invention is to provide a semiconductor differential circuit capable of miniaturizing an IC chip, an oscillation apparatus using the semiconductor differential circuit, an amplifying apparatus using the semiconductor differential circuit and a switching apparatus using the semiconductor differential circuit, and a semiconductor differential circuit placement method.

SUMMARY OF THE INVENTION

[0015] The 1^(st) aspect of the present invention is a semiconductor differential circuit comprising:

[0016] a semiconductor substrate,

[0017] a first semiconductor device formed on said semiconductor substrate, having a first gate electrode for having one of differential signals conveyed thereto and a first drain electrode for outputting one of the differential signals controlled by said first gate electrode;

[0018] a second semiconductor device formed on said semiconductor substrate, having a second gate electrode for having the other of said differential signals conveyed thereto and a second drain electrode for outputting the other of the differential signals controlled by said second gate electrode, and wherein:

[0019] said first drain electrode and said second drain electrode are placed in the proximity so that, at a predetermined frequency, it is equivalent to the one in which said first drain electrode is grounded via a first predetermined resistance, and said second drain electrode is grounded via a resistance of the same resistance value as said first predetermined resistance.

[0020] The 2^(nd) aspect of the present invention is the semiconductor differential circuit according to the 1^(st) aspect of the present invention, wherein the resistance value of said first predetermined resistance is half the resistance value formed between said first drain electrode and said second drain electrode via said semiconductor substrate, which is determined by space between said first drain electrode and said second drain electrode at said predetermined frequency.

[0021] The 3^(rd) aspect of the present invention is the semiconductor differential circuit according to the 1^(st) aspect of the present invention, wherein said first semiconductor device and said second semiconductor device are multi-finger type FETs respectively, and are placed so that a longitudinal direction of said second drain electrode is along and in the proximity of the longitudinal direction of said first drain electrode.

[0022] The 4^(th) aspect of the present invention is the semiconductor differential circuit according to the 3^(rd) aspect of the present invention, wherein:

[0023] as to said first semiconductor device:

[0024] said first gate electrode is placed to be adjacent to said first drain electrode along the longitudinal direction of said first drain electrode; and

[0025] it has a first source electrode placed to be adjacent to said first gate electrode along the longitudinal direction of said first gate electrode, and

[0026] as to said second semiconductor device:

[0027] said second gate electrode is placed to be adjacent to said second drain electrode along the longitudinal direction of said second drain electrode; and

[0028] it has a second source electrode placed to be adjacent to said second gate electrode along the longitudinal direction of said second gate electrode, and

[0029] a circuit comprising said first semiconductor device and said second semiconductor device is provided as a first unit circuit;

[0030] n pieces of said first unit circuit are placed to be mutually adjacent;

[0031] an i+1-th first unit circuit is placed to be adjacent to an i-th (i is between 1 and n−1) first unit circuit; and

[0032] said n pieces of first drain electrode are mutually connected, said n pieces of second drain electrode are mutually connected, said n pieces of first gate electrode are mutually connected, said n pieces of second gate electrode are mutually connected, and said n pieces of first source electrode and said n pieces of second source electrode are mutually connected.

[0033] The 5^(th) aspect of the present invention is the semiconductor differential circuit according to the 3^(rd) aspect of the present invention, wherein:

[0034] a third source electrode is formed on said semiconductor substrate;

[0035] said first gate electrode is placed to be adjacent to said third source electrode along the longitudinal direction of said third source electrode;

[0036] said first drain electrode is placed in the proximity of said first gate electrode on the opposite side to said third source electrode along the longitudinal direction of said first gate electrode;

[0037] said second drain electrode is placed to be adjacent to said first drain electrode on the opposite side to said first gate electrode along the longitudinal direction of said first drain electrode;

[0038] said second gate electrode is placed to be adjacent to said second drain electrode on the opposite side to said first drain electrode along the longitudinal direction of said second drain electrode, and

[0039] a circuit comprising said third source electrode, said first gate electrode, said first drain electrode, said second drain electrode and said second gate electrode is provided as a second unit circuit;

[0040] n pieces of said second unit circuit are placed to be mutually adjacent;

[0041] said second gate electrode of the i-th (i is between 1 and n−1) second unit circuit is placed to be adjacent to said third source electrode of the i+1-th second unit circuit; and

[0042] said n pieces of first drain electrode are mutually connected, said n pieces of second drain electrode are mutually connected, said n pieces of first gate electrode are mutually connected, said n pieces of second gate electrode are mutually connected, and said n pieces of third source electrode are mutually connected.

[0043] The 6^(th) aspect of the present invention is the semiconductor differential circuit according to the 1^(st) aspect of the present invention, wherein:

[0044] said first gate electrode is placed to surround said first drain electrode;

[0045] said second gate electrode is placed to surround said second drain electrode; and

[0046] a source electrode is placed between said first gate electrode and said second gate electrode.

[0047] The 7^(th) aspect of the present invention is the semiconductor differential circuit according to the 6^(th) aspect of the present invention, wherein:

[0048] there are two pieces each of said first drain electrode and said second drain electrode;

[0049] a source electrode is placed between one first drain electrode and one second drain electrode;

[0050] an electrode connected to said source electrode is placed between the other first drain electrode and the other second drain electrode;

[0051] an electrode connected to said source electrode is placed between one first drain electrode and the other second drain electrode; and

[0052] an electrode connected to said source electrode is placed between the other first drain electrode and said one second drain electrode.

[0053] The 8^(th) aspect of the present invention is the semiconductor differential circuit according to the 1^(st) or the 2^(nd) aspects of the present invention, wherein:

[0054] said first gate electrode.is placed to be adjacent to said first drain electrode;

[0055] said second gate electrode is placed to be adjacent to said second drain electrode; and

[0056] a source electrode is placed to surround said first drain electrode, said second drain electrode, said first gate electrode and said second gate electrode and to be adjacent to said first gate electrode and said second gate electrode.

[0057] The 9^(th) aspect of the present invention is the semiconductor differential circuit according to the 8^(th) aspect of the present invention, wherein there are two pieces each of said first drain electrode and said second drain electrode, and one first drain electrode and one second drain electrode are placed to be in proximity, the other first drain electrode and the other second drain electrode are placed to be in proximity, said one first drain electrode and said other second drain electrode are placed to be in proximity, and said other first drain electrode and said one second drain electrode are placed to be in proximity.

[0058] The 10^(th) aspect of the present invention is a semiconductor differential circuit comprising:

[0059] a semiconductor substrate,

[0060] a first semiconductor device, formed on said semiconductor substrate, having a first collector or base for having one of differential signals conveyed thereto; and

[0061] a second semiconductor device, formed on said semiconductor substrate, having a second collector or base for having the other of said differential signals conveyed thereto, and wherein:

[0062] said first collector or base and said second collector or base are placed in the proximity so that, at a predetermined frequency, it is equivalent to the one in which said first collector or base is grounded via a second predetermined resistance, and said second collector or base is grounded via a resistance of the same resistance value as said second predetermined resistance.

[0063] The 11^(th) aspect of the present invention is an oscillation apparatus using the semiconductor differential circuit according to the 1^(st) or the 10^(th) aspects of the present invention.

[0064] The 12^(th) aspect of the present invention is a switching apparatus using the semiconductor differential circuit according to the 1^(st) or the 10^(th) aspects of the present invention.

[0065] The 13^(th) aspect of the present invention is an amplifying apparatus using the semiconductor differential circuit according to the 1^(st) or the 10^(th) aspects of the present invention.

[0066] The 14^(th) aspect of the present invention is a semiconductor differential circuit placement method comprising the steps of:

[0067] forming on a semiconductor substrate a first semiconductor device having a first drain electrode for having one of differential signals conveyed thereto and a first gate electrode for controlling said one of the signals;

[0068] forming on said semiconductor substrate a second semiconductor device having a second drain electrode for having the other of said differential signals conveyed thereto and a second gate electrode for having said other signal conveyed thereto formed, and wherein:

[0069] said first drain electrode and said second drain electrode are placed in the proximity so that, at a predetermined frequency, it is equivalent to the one in which said first drain electrode is grounded via a first predetermined resistance, and said second drain electrode is grounded via a resistance of the same resistance value as said first predetermined resistance.

[0070] The 15^(th) aspect of the present invention is the semiconductor differential circuit according to the 1^(st) aspect of the present invention, wherein:

[0071] it further comprises:

[0072] a third semiconductor device, formed on said semiconductor substrate, having a second gate electrode for having the other of said differential signals conveyed thereto, and a first drain electrode for outputting one of the differential signals controlled by said second gate electrode; and

[0073] a fourth semiconductor device, formed on said semiconductor substrate, having a first gate electrode for having one of said differential signals conveyed thereto, and a second drain electrode for outputting the other of the differential signals controlled by said first gate electrode, and

[0074] the differential signals conveyed to said first gate electrode and said second gate electrode are differential local oscillation signals;

[0075] said first semiconductor device has a first source electrode for having one of the differential signals to be mixed with said differential local oscillation signals conveyed thereto;

[0076] said second semiconductor device shares said first source electrode with said first semiconductor device;

[0077] said third semiconductor device shares said first drain electrode with said first semiconductor device, and has a second source electrode for having the other of the differential signals to be mixed with said differential local oscillation signals conveyed thereto;

[0078] said fourth semiconductor device shares said second source electrode with said third semiconductor device, and shares said second drain electrode with said second semiconductor device;

[0079] said differential signals controlled by said second gate electrode are the differential signals having said differential local oscillation signals and said differential signals to be mixed mixed therein; and

[0080] said first drain electrode and said second drain electrode are placed in the proximity so that, at a frequency of said mixed differential signals, it is equivalent to the one in which said first.drain electrode is grounded via a first predetermined resistance, and said second drain electrode is grounded via a resistance of the same resistance value as said first predetermined resistance.

[0081] The 16^(th) aspect of the present invention is the semiconductor differential circuit according to the 15^(th) aspect of the present invention, wherein:

[0082] said first gate electrode and said second gate electrode are placed in the proximity so that, at a frequency of said differential local oscillation signals, it is equivalent to the one in which said first gate electrode is grounded via a third predetermined resistance, and said second gate electrode is grounded via a resistance of the same resistance value as said third predetermined resistance; and

[0083] said first source electrode and said second source electrode are placed in the proximity so that, at a frequency of the differential signals to be mixed with said differential local oscillation signals, it is equivalent to the one in which said first source electrode is grounded via a fourth predetermined resistance, and said second source electrode is grounded via a resistance of the same resistance value as said fourth predetermined resistance.

[0084] The 17^(th) aspect of the present invention is the semiconductor differential circuit according to the 15^(th) aspect of the present invention, wherein the resistance value of said first predetermined resistance is half the resistance value formed between said first drain electrode and said second drain electrode via said semiconductor substrate, which is determined by space between said first drain electrode and said second drain electrode at the frequency of said mixed differential signals.

[0085] The 18^(th) aspect of the present invention is the semiconductor differential circuit according to the 16^(th) aspect of the present invention, wherein the resistance value of said third predetermined resistance is half the resistance value formed between said first gate electrode and said second gate electrode via said semiconductor substrate, which is determined by space between said first gate electrode and said second gate electrode at the frequency of said differential local oscillation signals.

[0086] The 19^(th) aspect of the present invention is the semiconductor differential circuit according to the 16^(th) aspect of the present invention, wherein the resistance value of said fourth predetermined resistance is half the resistance value formed between said first source electrode and said second source electrode via said semiconductor substrate, which is determined by space between said first source electrode and said second source electrode at the frequency of the differential signals to be mixed.

[0087] The 20^(th) aspect of the present invention is the semiconductor differential circuit according to the 15^(th) aspect of the present invention, wherein said first semiconductor device, said second semiconductor device, said third semiconductor device and said fourth semiconductor device are multi-finger type FETs respectively, and are placed so that a longitudinal direction of said second drain electrode is along and in the proximity of the longitudinal direction of said first drain electrode.

[0088] The 21^(st) aspect of the present invention is the semiconductor differential circuit according to the 16^(th) aspect of the present invention, wherein said first semiconductor device, said second semiconductor device, said third semiconductor device and said fourth semiconductor device are multi-finger type FETs respectively, and are placed so that a longitudinal direction of said second gate electrode is along and in the proximity of the longitudinal direction of said first gate electrode.

[0089] The 22^(nd) aspect of the present invention is the semiconductor differential circuit according to the 16^(th) aspect of the present invention, wherein said first semiconductor device, said second semiconductor device, said third semiconductor device and said fourth semiconductor device are multi-finger type FETs respectively, and are placed so that a longitudinal direction of said second source electrode is along and in the proximity of the longitudinal direction of said first source electrode.

[0090] The 23^(rd) aspect of the present invention is the semiconductor differential circuit according to any one of the 20^(th) to the 22^(nd) aspects of the present invention, wherein:

[0091] the first source electrode is formed on said semiconductor substrate;

[0092] said first gate electrode is placed to be adjacent to said first source electrode along the longitudinal direction of said first source electrode; and

[0093] said first drain electrode is placed to be adjacent to said first gate electrode on the opposite side to said first source electrode along the longitudinal direction of said first gate electrode;

[0094] said second gate electrode is placed to be adjacent to said first drain electrode on the opposite side to said first gate electrode along the longitudinal direction of said first drain electrode;

[0095] said second source electrode is placed to be adjacent to said second gate electrode on the opposite side to said first drain electrode along the longitudinal direction of said second gate electrode;

[0096] said first gate electrode is placed to be adjacent to said second source electrode on the opposite side to said second gate electrode along the longitudinal direction of said second source electrode;

[0097] said second drain electrode is placed to be adjacent to said first gate electrode on the opposite side to said second source electrode along the longitudinal direction of said first gate electrode;

[0098] said second gate electrode is placed to be adjacent to said second drain electrode on the opposite side to said first gate electrode along the longitudinal direction of said second drain electrode, and

[0099] a circuit having said first source electrode, said second source electrode, said first gate electrode, said second gate electrode, said first drain electrode and said second drain electrode is provided as a third unit circuit;

[0100] n pieces of said third unit circuit are placed to be mutually adjacent;

[0101] said second gate electrode of an i-th (i is between 1 and n−1) third unit circuit is placed to be adjacent to said first source electrode of an i+1-th third unit circuit; and

[0102] said n pieces of first drain electrode are mutually connected, said n pieces of second drain electrode are mutually connected, said n pieces of first gate electrode are mutually connected, said n pieces of second gate electrode are mutually connected, said n pieces of first source electrode are mutually connected, and said n pieces of second source electrode are mutually connected.

[0103] The 24^(th) aspect of the present invention is a mixer apparatus using the semiconductor differential circuit according to any one of the 1^(st), the 10^(th) and the 15^(th) aspects of the present invention.

[0104] The 25^(th) aspect of the present invention is a circuit apparatus sharing an FET source, using the semiconductor differential circuit according to the 1^(st) aspect of the present invention.

[0105] According to the present invention, it is possible to provide the semiconductor differential circuit capable of miniaturizing the IC chip, oscillation apparatus using the semiconductor differential circuit, amplifying apparatus using the semiconductor differential circuit and switching apparatus using the semiconductor differential circuit and semiconductor differential circuit placement method.

BRIEF DESCRIPTION OF THE DRAWINGS

[0106]FIG. 1(a) is a plan view showing a configuration of a semiconductor differential circuit according to a first embodiment of the present invention.

[0107]FIG. 1(b) is a sectional view showing the configuration of the semiconductor differential circuit according to the first embodiment of the present invention.

[0108]FIG. 2(a) is a plan view showing the configuration of the semiconductor differential circuit according to a second embodiment of the present invention.

[0109]FIG. 2(b) is a sectional view showing the configuration of the semiconductor differential circuit according to the second embodiment of the present invention.

[0110]FIG. 3 is a plan view showing the configuration of the semiconductor differential circuit according to a third embodiment of the present invention.

[0111]FIG. 4 is a plan view showing the configuration of the semiconductor differential circuit according to the third embodiment of the present invention.

[0112]FIG. 5 is a plan view showing the configuration of the semiconductor differential circuit according to the third embodiment of the present invention.

[0113]FIG. 6(a) is a sectional view showing the configuration of the semiconductor differential circuit according to a fourth embodiment of the present invention.

[0114]FIG. 6(b) is a sectional view showing the configuration of the semiconductor differential circuit according to the fourth embodiment of the present invention.

[0115]FIG. 7 is a plan view showing the configuration of the semiconductor differential circuit according to the fourth embodiment of the present invention.

[0116]FIG. 8 is a plan view showing the configuration of the semiconductor differential circuit according to the fourth embodiment of the present invention.

[0117]FIG. 9 is a plan view showing another configuration of the semiconductor differential circuit according to the first embodiment of the present invention.

[0118]FIG. 10 is a diagram showing a circuit configuration of an oscillation apparatus using the semiconductor differential circuit of the present invention.

[0119]FIG. 11 is a diagram showing the circuit configuration of an amplifier apparatus using the semiconductor differential circuit of the present invention.

[0120]FIG. 12 is a diagram showing the circuit configuration of the oscillation apparatus of the prior art.

[0121]FIG. 13 is a diagram showing the circuit configuration of the amplifier apparatus of the prior art.

[0122]FIG. 14 shows an equivalent circuit of a circuit element considering influence of a parasitic component in the oscillation apparatus or amplifier apparatus of the prior art.

[0123]FIG. 15 is a diagram showing the influence of change in a Q-value on a resonance frequency characteristic of a resonant circuit used for the oscillation apparatus of the present invention or the prior art.

[0124]FIG. 16 is a diagram showing the influence of a parasitic resistance on a Q-value of the resonant circuit used for the oscillation apparatus of the present invention or the prior art.

[0125]FIG. 17 is a plan view showing the configuration of a multi-finger type FET of the prior art.

[0126]FIG. 18 is a plan view showing a placement when the multi-finger type FET of the prior art has a differential configuration.

[0127]FIG. 19 is a circuit diagram showing the configuration of a mixer apparatus using the semiconductor differential circuit according to a fifth embodiment of the present invention.

[0128]FIG. 20(a) is a plan view showing the configuration of the semiconductor differential circuit according to the fifth embodiment of the present invention.

[0129]FIG. 20(b) is a sectional view showing the configuration of the semiconductor differential circuit according to the fifth embodiment of the present invention.

DESCRIPTION OF SYMBOLS

[0130]1 Semiconductor substrate

[0131]2 Parasitic capacitance

[0132]3 Parasitic resistance

[0133]4 Electrical midpoint

[0134] D1, D1′, D2, D2′ Drain electrodes

[0135] G1, G1′, G2, G2′ Gate electrodes

[0136] S, S1, S2, S3 Source electrodes

[0137]11, 12, 13 Semiconductor differential circuits

PREFERRED EMBODIMENTS OF THE INVENTION

[0138] (First Embodiment)

[0139]FIG. 1 is a plan view (FIG. 1(a)) and a sectional view (FIG. 1(b)) of a multi-finger type semiconductor differential circuit according to a first embodiment of the present invention. The semiconductor differential circuit shown in FIG. 1 has a first drain electrode D1 in a longitudinal shape placed on a semiconductor substrate 1, a gate electrode G1 in a longitudinal shape which is an example of a first gate electrode of the present invention is placed to be adjacent to the drain electrode D1 on both sides of the drain electrode D1, and a source electrode S in a longitudinal shape which is an example of a first source electrode of the present invention is placed to be adjacent to each gate electrode G1. To be more specific, a configuration having the source electrode S, gate electrode G1, drain electrode D1, gate electrode G1 and source electrode S is an example showing the configuration of a first semiconductor device of the present invention.

[0140] A second drain electrode D2 in a longitudinal shape is placed on the semiconductor substrate 1, a gate electrode G2 in a longitudinal shape which is an example of a second gate electrode of the present invention is placed to be adjacent to the drain electrode D2 on both sides of the drain electrode D2, and the source electrode S in the longitudinal shape which is an example of a second source electrode of the present invention is placed to be adjacent to each gate electrode G2. To be more specific, a configuration having the source electrode S, gate electrode G2, drain electrode D2, gate electrode G2 and source electrode S is an example showing the configuration of a second semiconductor device of the present invention.

[0141] Here, if the above circuit comprising the first semiconductor device and second semiconductor device of the present invention is a first unit circuit, the circuit shown in FIG. 1 has the configuration in which a 1st first unit circuit and a 2nd first unit circuit are adjacently placed. In FIG. 1, the source electrode S at the right edge of the first semiconductor device and the source electrode S at the left edge of the second semiconductor device are shared. And the source electrode S at the right edge of the 1st first unit circuit and the source electrode S at the left edge of the 2nd first unit circuit are shared.

[0142] In this case, the drain electrode D1 and drain electrode D2 are placed as close as possible. One of differential signals is inputted to the drain electrode D1, and the other of the differential signals is inputted to the drain electrode D2. In the first unit circuit, the drain electrodes D1 are mutually connected, the drain electrodes D2 are mutually connected, the gate electrodes G1 are mutually connected, and the gate electrodes G2 are mutually connected.

[0143] Next, operation of the semiconductor differential circuit constituted as above and illustrated in FIG. 1 will be described. One of the differential signals is conveyed to the drain electrode D1, and the other of the differential signals is conveyed to the drain electrode D2. Then, at a point where electrical lengths from the drain electrodes D1 and D2 are equal (hereafter referred to as an electrical midpoint), it becomes equivalent to being grounded because the differential signals counteract each other. To describe it by referring to FIG. 1(b) for instance, it can be considered that the drain electrodes D1 and D2 are connected via a parasitic capacitance 2 and a parasitic resistance 3 in a high-frequency area. As the drain electrodes D1 and D2 are formed in the same process on the semiconductor substrate 1, it can be considered that the parasitic capacitances 2 thereof are equal. Therefore, it is equivalent to being grounded (hereafter referred to as virtual grounding) at a midpoint of the parasitic resistance 3 between the drain electrodes D1 and D2 via the semiconductor substrate 1 or at an electrical midpoint 4 of the drain electrodes D1 and D2 inside the semiconductor substrate 1. Thus, if the resistance determined by space between the drain electrodes D1 and D2 inside the semiconductor substrate 1 is R, the drain electrodes D1 and D2 are equivalent to being grounded via resistance of R/2 (corresponding to a first predetermined resistance value of the present invention) respectively.

[0144] Thus, the semiconductor differential circuit according to this embodiment can connect to ground without requiring the contactors 1035 connected to the grounding side, and no longer needs grounding area for the contactors 1035 and silicon substrate wiring 1036 so that the IC chip can be miniaturized. Furthermore, the value of the parasitic resistance 3 can be reduced to a half, and so the resistance value thereof can further be reduced. Consequently, a Q-value of a resonator can be increased so as to improve the characteristic deterioration of an oscillation apparatus and an amplifying apparatus.

[0145] It was described that, in the configuration shown in FIG. 1, the first semiconductor device has the configuration in which the gate electrodes G1 are placed on both sides of the drain electrode D1 respectively. However, the first semiconductor device may have the configuration in which the gate electrode G1 is placed on one side of the drain electrode D1. In that case, the first semiconductor device has one source electrode adjacent to the gate electrode G1. The second semiconductor device also has the same configuration as the first semiconductor device.

[0146] According to the above description, in the first unit circuit, the drain electrodes D1 are mutually connected, the drain electrodes D2 are mutually connected, the gate electrodes G1 are mutually connected, and the gate electrodes G2 are mutually connected. However, it is also possible to consider the configuration in which the drain electrodes D1 are not mutually connected, the drain electrodes D2 are not mutually connected, the gate electrodes G1 are not mutually connected, and the gate electrodes G2 are not mutually connected. In that case, it may be the configuration in which the 1st first unit circuit is connected in series to the 2nd first unit circuit. To be more specific, it may be the configuration in which an output side of the first semiconductor device of the 1st first unit circuit is connected to an input side of the first semiconductor device of the 2nd first unit circuit, and the output side of the second semiconductor device of the 1st first unit circuit is connected to the input side of the second semiconductor device of the 2nd first unit circuit.

[0147] The above showed the case of having the configuration in which two first unit circuits are connected. However, it may also be the configuration in which n pieces (n is 2 or more) of the first unit circuit are connected. In that case, it should be the configuration in which an i+1-th first unit circuit is placed to be adjacent to an i-th (i is between 1 and n−1) first unit circuit.

[0148] (Second Embodiment)

[0149]FIG. 2 is a plan view (FIG. 2(a)) and a sectional view (FIG. 2(b)) showing the configuration of the multi-finger type semiconductor differential circuit according to a second embodiment of the present invention. The semiconductor differential circuit shown in FIG. 2 has the source electrode S which is an example of a third source electrode of the present invention formed on the semiconductor substrate 1, the gate electrode G1 which is an example of the first gate electrode of the present invention placed to be adjacent to the source electrode S along the longitudinal direction of the source electrode S, the drain electrode D1 which is an example of the first drain electrode of the present invention placed to be adjacent to the gate electrode G1 on the opposite side to the source electrode S along the longitudinal direction of the gate electrode G1, the drain electrode D2 which is an example of the second drain electrode of the present invention placed close to the drain electrode D1 on the opposite side to the gate electrode G1 along the longitudinal direction of the drain electrode D1, and the gate electrode G2 which is an example of the second gate electrode of the present invention placed to be adjacent to the drain electrode D2 on the opposite side to the drain electrode D1 along the longitudinal direction of the drain electrode D2.

[0150] The configuration in which the source electrode S, gate electrode G1, drain electrode D1, drain electrode D2 and gate electrode G2 are arranged is an example of how a second unit circuit of the present invention is formed.

[0151] In the second unit circuit, the drain electrodes D1 are mutually connected, the drain electrodes D2 are mutually connected, the gate electrodes G1 are mutually connected, and the gate electrodes G2 are mutually connected.

[0152] According to the semiconductor differential circuit of this embodiment, no other electrode is inserted between the drain electrode D1 and drain electrode D2, and so the drain electrode D1 and drain electrode D2 can be placed closer than those in the case of the semiconductor differential circuit of the first embodiment so as to further improve the Q-value of the resonator. Therefore, the semiconductor differential circuit of this embodiment can further improve the characteristic deterioration of the oscillation apparatus and amplifying apparatus.

[0153] The configuration shown in FIG. 2 shows an example in which two second unit circuits are placed. However, the semiconductor differential circuit of this embodiment may be comprising n pieces (n is 2 or more) of second unit circuit. In that case, an i+1-th second unit circuit should be placed to be adjacent to an i-th (i is between 1 and n−1) second unit circuit. And the gate electrode G2 of the i-th second unit circuit should be placed to be adjacent to the source electrode S of the i+1-th unit circuit.

[0154] In the above description of the first and second embodiments, it was described that the drain electrode D1 and drain electrode D2 are placed to be close in the longitudinal direction. However, the drain electrode D1 and drain electrode D2 maybe close in another direction. For instance, FIG. 9 shows the configuration in which the end portions of the drain electrode D1 and drain electrode D2 are close. Even in such a configuration, the electrical midpoint (that is, a distance midpoint) of the drain electrodes D1 and D2 is a virtual grounding point, and both the drain electrode D1 and drain electrode D2 are equivalent to the state of being connected to the grounding side via the parasitic resistance value R/2 so as to obtain the same effect as in the above case.

[0155] In the second unit circuit, the drain electrodes D1 are mutually connected, the drain electrodes D2 are mutually connected, the gate electrodes G1 are mutually connected, and the gate electrodes G2 are mutually connected. However, it is also possible to consider the configuration in which the drain electrodes D1 are not mutually connected, the drain electrodes D2 are not mutually connected, the gate electrodes G1 are not mutually connected, and the gate electrodes G2 are not mutually connected. In that case, the 1st second unit circuit may be connected in series to the 2nd second unit circuit. To be more specific, it may be the configuration in which the output side of the first semiconductor device of the 1st second unit circuit is connected to the input side of the first semiconductor device of the 2nd second unit circuit, and the output side of the second semiconductor device of the 1st second unit circuit is connected to the input side of the second semiconductor device of the 2nd second unit circuit.

[0156] The FETs according to the above description were the multi-finger type. However, they may also be the FETs of another type, and the same effect as above can be obtained in that case.

[0157] (Third Embodiment)

[0158]FIG. 3 is a plan view showing the configuration of the semiconductor differential circuit according to a third embodiment of the present invention. The semiconductor differential circuit shown in FIG. 3 has the drain electrode D1 and drain electrode D1′ which are examples of rectangular first drain electrodes of the present invention and the drain electrode D2 and drain electrode D2′ which are examples of rectangular second electrodes of the present invention. And it has the gate electrode G1 and gate electrodes G1′ which are examples of the first gate electrodes of the present invention and placed to surround the drain electrodes D1 and D1′ respectively and the gate electrode G2 and gate electrodes G2′ which are examples of the second gate electrodes of the present invention and placed to surround the drain electrodes D2 and D2′ respectively.

[0159] And a source electrode S1 in a longitudinal shape is placed between the gate electrode G1 and gate electrode G1′ and between the gate electrode G2 and gate electrode G2′, and a source electrode S2 in a longitudinal shape connected to the source electrode S1 to cross it is placed between the gate electrode G1 and gate electrodes G2 and between the gate electrode G1′ and gate electrodes G2′.

[0160] And a source electrode S3 is placed to surround the gate electrodes G1, G1′, G2, G2′ and the source electrodes S1, S2. The source electrode S1 and S2 are connected to the source electrode S3. The source electrode shown in FIG. 3 formed by the source electrodes S1, S2 and S3 is constituted as an example of the source electrode of the present invention.

[0161] Here, the drain electrode D1 and drain electrode D2 are placed close so that the midpoint (or a midline) connecting them becomes a virtual grounding point (or a virtual grounding line). The drain electrode D1′ and D2′ are also placed close likewise. Therefore, the above virtual grounding line extends up and down approximately along the source electrode S2.

[0162] According to such a semiconductor differential circuit of this embodiment, each drain electrode has only to be surrounded by each gate electrode. Therefore, each drain electrode can be constituted with sufficiently small area. It is possible, by rendering the area of each drain electrode smaller, to reduce the parasitic capacitance 2 with the semiconductor substrate 1 so as to constitute an oscillating circuit and the amplifier circuit with further reduced characteristic deterioration.

[0163] In the above description, it was described that the virtual grounding line is along the source electrode S2. However, the virtual grounding line may also be formed along the source electrode S1.

[0164] Furthermore, the virtual grounding line may also be formed along the source electrode S1 and source electrode S2 respectively. FIG. 4 shows the configuration in that case. The semiconductor differential circuit shown in FIG. 4 has the configuration in which the drain electrode D1 and drain electrode D1′ of the semiconductor differential circuit shown in FIG. 3 are diagonally placed, and the drain electrode D2 and drain electrode D2′ are diagonally placed. To be more specific, the source electrode S2 is placed between the drain electrode D1 which is an example of one of the first drain electrodes of the present invention and the drain electrode D2 which is an example of one of the second drain electrodes of the present invention, the source electrode S2 is placed between the drain electrode D1′ which is an example of the other of the first drain electrodes of the present invention and the drain electrode D2′ which is an example of the other of the second drain electrodes of the present invention, the source electrode S1 connected to the source electrode S2 is placed between the drain electrode D1 and the drain electrode D2′, and the source electrode S1 is placed between the drain electrode D1′ and the drain electrode D2.

[0165] A virtual midline is formed approximately along the source electrode S2 and source electrode S1 by thus placing the drain electrodes. The virtual midline is thereby increased so that the drains and the grounding side are connected via the parasitic resistance value R/2 in a wider range. For this reason, it is possible, according to the semiconductor differential circuit shown in FIG. 4, to constitute the oscillating circuit and amplifier circuit with further reduced characteristic deterioration.

[0166] According to the above description of this embodiment, the drain electrodes are rectangular. However, the drain electrodes may be in any shape as long as they are surrounded by the gate electrodes. And the same effect as above can be obtained in that case.

[0167] According to the above description, there four drain electrodes in the configuration in the example in FIG. 3 for instance. However, it may be a different number of pieces. In that case, the gate electrodes should be placed to surround the drain electrodes, and the source electrode should be placed between the first gate electrode and second gate electrode. And same effect as above can be obtained in that case.

[0168] The configuration shown in FIG. 5 has the source electrode S1 and source electrode S2 eliminated from the configuration shown in FIG. 4. In the configuration shown in FIG. 5, the shape of each gate electrode is not the one for surrounding each drain electrode, but each gate electrode is placed to be sandwiched by each drain electrode and the source electrode S3. To be more specific, the drain electrode D1 which is an example of one of the first drain electrode of the present invention and the drain electrode D2 which is an example of one of the second drain electrode of the present invention are placed close, the drain electrode D1′ which is an example of the other of the first drain electrode of the present invention and the drain electrode D2′ which is an example of the other of the second drain electrode of the present invention are placed close, the drain electrode D1 and drain electrode D2′ are placed close, and the drain electrode D1′ and drain electrode D2 are placed close.

[0169] According to the semiconductor differential circuit of such a configuration, the source electrodes S1 and S2 do not exist among the drain electrodes. Therefore, it is possible to place the drain electrodes closer so as to further reduce the parasitic resistance 3. Thus, it is possible, by using the semiconductor differential circuit shown in FIG. 5, to provide the oscillating circuit and amplifier circuit with further reduced characteristic deterioration. In this case, the numbers, shapes and placements of the drain electrodes are not limited to those shown in FIG. 5, but other numbers, shapes and placements may be taken and the same effect as above can be obtained in that case as long as the first drain electrode and second drain electrode are placed close and the source electrodes are placed to surround the drain electrodes and gate electrodes.

[0170] (Fourth Embodiment)

[0171]FIG. 6 is a sectional view showing the configuration of the semiconductor differential circuit according to a fourth embodiment of the present invention. The semiconductor differential circuit of this embodiment is the semiconductor differential circuit according to the first to third embodiments constituted by bipolar transistors. As for the semiconductor differential circuit shown in FIG. 6(a), a collector C1 as an example of a first collector of the present invention is formed like a well on the semiconductor substrate 1, a base B1 as an example of a first base of the present invention is formed like a well on the collector C1, and an emitter E is formed like a well on the base B1. In this case, one of the differential signals is inputted to the collector C1, and the collector C1, base B1 and emitter E are forming the first semiconductor device of the present invention.

[0172] A collector C2 as an example of a second collector of the present invention is formed like a well next to the collector C1, a base B2 as an example of a second base of the present invention is formed like a well on the collector C2, and the emitter E is formed like a well on the base B2. In this case, the other of the differential signals is inputted to the collector C2, and the collector C2, base B2 and emitter E are forming the second semiconductor device of the present invention. And an insulating layer 5 is provided between the collector C1 and collector C2, but the collector C1 and collector C2 are placed as close as possible. The first semiconductors and second semiconductors are placed so that the collectors thereof are repeatedly placed in order of C1, C2, C2 and C1.

[0173] Consequently, the collector C1 becomes equivalent, as to a high-frequency signal component, to being grounded at a parasitic resistance value R′/2 (corresponding to a second predetermined resistance value of the present invention) which is half the parasitic resistance value R′ determined by the distance of the collector C1 and collector C2 in the semiconductor substrate 1, and the collector C2 likewise becomes equivalent to being grounded at the parasitic resistance value R′/2. Consequently, the Q-value of the resonant circuit can be increased as in the cases of the first to third embodiments.

[0174]FIG. 6(b) shows the semiconductor differential circuit constituted by bipolar transistors of another example. As for the semiconductor differential circuit shown in FIG. 6(b), the first semiconductor and second semiconductor are placed so that the collectors thereof are repeatedly placed in order of C1, C2, C1 and C2. According to such a configuration, more electrical midpoints 4′ are formed compared to the case according to the configuration shown in FIG. 6(a) so as to provide the oscillator and amplifier with further reduced characteristic deterioration.

[0175] The above described the configuration in which each collector is formed as a well on the semiconductor substrate 1. However, it may also be the configuration in which each base is formed as a well on the semiconductor substrate 1. In that case, each base is placed at the position of each collector in FIGS. 6(a) and 6(b), each emitter is placed at the position of each base, and each collector is placed at the position of each emitter. FIG. 7 shows a plan view of the semiconductor differential circuit shown from above in such a case. And it is the configuration in which the base B1 as an example of the first base of the present invention and the base B2 as an example of the second base of the present invention are close, where the same effect as above can be obtained.

[0176] It is also thinkable, as shown in FIG. 8, to diagonally place the base B1 and base B1′ to which one of the differential signals is conveyed and diagonally place the base B2 and base B2′ to which the other of the differential signals is conveyed. The same effect as above can be obtained from such a configuration.

[0177] The oscillation apparatus and amplifying apparatus using the semiconductor differential circuits described in the first to fourth embodiments belong to the category of the present invention. FIG. 10 shows an example of circuit configuration of the oscillation apparatus using the semiconductor differential circuit of the present invention. In the circuit shown in FIG. 10, the portion comprising switching elements 1006 and 1007 in the circuit shown in FIG. 12 is replaced by a semiconductor differential circuit 11 of the present invention, and the portion comprising MOSFETs 1010 and 1020 therein is replaced by a semiconductor differential circuit 12 of the present invention. The semiconductor differential circuit 11 has a control voltage terminal 13 connected thereto, and is capable of switching a frequency band of an oscillation frequency with control voltage applied to a control voltage terminal 13. The semiconductor differential circuit 12 has a reduced parasitic resistance value as described above so that the Q-value of the resonant circuit can be increased enough to curb the characteristic deterioration of the oscillating circuit.

[0178]FIG. 11 shows a circuit configuration example of the amplifying apparatus using the semiconductor differential circuit of the present invention. In the circuit shown in FIG. 11, the portion comprising MOSFETs 1030 and 1031 in the circuit shown in FIG. 13 is replaced by a semiconductor differential circuit 13 of the present invention. Such an amplifying apparatus can reduce the loss due to the parasitic resistance and curb the characteristic deterioration of the amplifying apparatus as described above.

[0179] In the case of using the semiconductor differential circuit of the present invention as a switching apparatus, it is possible to reduce the loss due to the parasitic resistance and parasitic capacitance when the switching element is on. It is also possible, in the case of using the switching apparatus and the above-mentioned oscillation apparatus in combination for instance, to curb the characteristic deterioration of the oscillating circuit.

[0180] (Fifth Embodiment)

[0181] The semiconductor differential circuit according to a fifth embodiment of the present invention will be described. FIG. 19 shows a circuit configuration of a double balance mixer. In FIG. 19, reference numerals 1901 and 1902 denote the bipolar transistors, 1903, 1904, 1905 and 1906 denote the MOSFETs corresponding to the first semiconductor device, second semiconductor device, third semiconductor device and fourth semiconductor device of the present invention respectively, 1907 denotes a constant current source, and 1908, 1909, 1910 and 1911 denote inductors. The differential signals are inputted from input nodes P1+ and P1−, and the inputted differential signals are amplified by the bipolar transistors 1901 and 1902. Output signals thereof (corresponding to the differential signals to be mixed with the differential local oscillation signals of the present invention) are inputted to each node connected to the source electrode S1 (corresponding to the first source electrode of the present invention) and the source electrode S2 (corresponding to the second source electrode of the present invention).

[0182] To be more specific, one of the output signals is inputted to the source electrode S1 shared by the MOSFETs 1903 and 1904, and the other of the output signals is inputted to the source electrode S2 shared by the MOSFETs 1905 and 1906.

[0183] Local oscillation signals (corresponding to the differential local oscillation signals of the present invention) inputted from the input nodes P3+ and P3− are inputted to each node connected to the gate electrode G1 (corresponding to the first gate electrode of the present invention) and gate electrode G2 (corresponding to the second gate electrode of the present invention), and are mixed in the MOSFETs 1903 to 1906. To be more specific, one of the local oscillation signals which are the differential signals is inputted to the gate electrode G1 shared by the MOSFETs 1903 and 1905, and the other of the local oscillation signals is inputted to the gate electrode G2 shared by the MOSFETs 1904 and 1906.

[0184] And one of the differential signals inputted from the source electrode S1 is controlled by one of the differential local oscillation signals inputted to the gate electrode G1 of the MOSFET 1903 so that a mixing signal of both (corresponding to a mixed differential signal of the present invention) is outputted as one of the differential signals from the drain electrode D1. And the other of the differential signals inputted from the source electrode S2 is controlled by the other of the differential local oscillation signals inputted to the gate electrode G2 of the MOSFET 1905 so that the mixing signal of both (corresponding to the mixed differential signal of the present invention) is outputted as one of the differential signals from the drain electrode D1.

[0185] Likewise, one of the differential signals inputted from the source electrode S1 is controlled by one of the differential local oscillation signals inputted to the gate electrode G2 of the MOSFET 1904 so that the mixing signal of both (corresponding to the mixed differential signal of the present invention) is outputted as the other of the differential signals from the drain electrode D2. And the other of the differential signals inputted from the source electrode S2 is controlled by one of the differential local oscillation signals inputted to the gate electrode G1 so that the mixing signal of both (corresponding to the mixed differential signal of the present invention) is outputted as the other of the differential signals from the drain electrode D2.

[0186] Thus, the signals frequency-converted by mixing are outputted to P2+ and P2− nodes from the MOSFETs 1903 to 1906.

[0187] Next, the configuration of the MOSFETs 1903 to 1906 will be described. FIG. 20(a) is a plan view of the MOSFETs 1903 to 1906, and Fig. 20(b) is a sectional view thereof. In these drawings, S1, S2, G1, G2, D1 and D2 are equivalent to the electrodes of the same reference numerals in FIG. 19. A unit cell (corresponding to the third unit circuit of the present invention) is in the broken line in FIG. 20(a), which is repeatedly placed.

[0188] To be more specific, the gate electrode G1 is placed to be adjacent to the source electrode S1 along the longitudinal direction of the source electrode S1, the drain electrode D1 is placed to be adjacent to the gate electrode G1 on the opposite side to the source electrode S1 along the longitudinal direction of the gate electrode G1, the gate electrode G2 is placed to be adjacent to the drain electrode D1 on the opposite side to the gate electrode G1 along the longitudinal direction of the drain electrode D1, the source electrode S2 is placed to be adjacent to the gate electrode G2 on the opposite side to the drain electrode D1 along the longitudinal direction of the gate electrode G2. The gate electrode G1 is placed to be adjacent to the source electrode S2 on the opposite side to the gate electrode G2 along the longitudinal direction of the source electrode S2, the drain electrode D2 is placed to be adjacent to the gate electrode G1 on the opposite side to the source electrode S2 along the longitudinal direction of the gate electrode G1. The gate electrode G2 is placed to be adjacent to the drain electrode D2 on the opposite side to the gate electrode G1 along the longitudinal direction of the drain electrode D2, a circuit having the source electrode S1, source electrode S2, gate electrode G1, gate electrode G2, drain electrode D1 and drain electrode D2 is provided as a third unit circuit, n pieces of the third unit circuit are placed to be mutually adjacent, the gate electrode G2 of the i-th (i is between 1 and n−1) third unit circuit is placed to be adjacent to the source electrode S1 of the i+1-th unit circuit, n pieces of the drain electrode D1 are mutually connected, n pieces of the drain electrode D2 are mutually connected, n pieces of the gate electrode G1 are mutually connected, n pieces of the gate electrode G2 are mutually connected, n pieces of the source electrode S1 are mutually connected, and n pieces of the source electrode S2 are mutually connected.

[0189] According to such a configuration, the gate electrodes G1 and G2 and the source electrodes S1 and S2 are symmetrically placed close in addition to the drain electrodes D1 and D2 which are a differential pair of outputs.

[0190] To be more specific, the drain electrodes D1 and D2 are placed close at the frequency of the mixed differential signal so that it is equivalent to the one in which the drain electrode D1 is grounded via the first predetermined resistance and the drain electrode D2 is grounded via the resistance of the same resistance value as the first predetermined resistance.

[0191] Here, the resistance value of the first predetermined resistance is half the resistance value formed between the drain electrode D1 and drain electrode D2 via the semiconductor substrate 1, which is determined by the space between the drain electrode D1 and drain electrode D2 at the frequency of the mixed differential signal.

[0192] Consequently, the loss on the silicon substrate from each node to a virtual ground is reduced so as to improve a noise characteristic and a distortion characteristic of the double balance mixer as in the case of the amplifier circuit.

[0193] Furthermore, the loss on the silicon substrate is further reduced and the noise characteristic and distortion characteristic of the double balance mixer are improved in the case where the gate electrodes G1 and G2 are placed close at the frequency of the predetermined differential local oscillation signals so that it is equivalent to the one in which the gate electrode G1 is grounded via the third predetermined resistance and the gate electrode G2 is grounded via the resistance of the same resistance value as the third predetermined resistance.

[0194] Here, the resistance value of the third predetermined resistance is half the resistance value formed between the gate electrode G1 and gate electrode G2 via the semiconductor substrate 1, which is determined by the space between the gate electrode G1 and gate electrode G2 at the frequency of the differential local oscillation signals.

[0195] Furthermore, the loss on the silicon substrate is further reduced and the noise characteristic and distortion characteristic of the double balance mixer are improved in the case where the source electrode S1 and source electrode S2 are placed close at the frequency of the differential signals to be mixed with the differential local oscillation signals so that it is equivalent to the one in which the source electrode S1 is grounded via the fourth predetermined resistance and the source electrode S2 is grounded via the resistance of the same resistance value as the fourth predetermined resistance.

[0196] Here, the resistance value of the fourth predetermined resistance is half the resistance value formed between the source electrode S1 and source electrode S2 via the semiconductor substrate 1, which is determined by the space between the source electrode S1 and source electrode S2 at the frequency of the above described differential signals to be mixed.

[0197] According to this embodiment, the first semiconductor device, second semiconductor device, third semiconductor device and fourth semiconductor device are the multi-finger type FETs in a typical case respectively. The longitudinal direction of the drain electrode D2 is placed along and in the proximity of the longitudinal direction of the drain electrode D1. In the case where the gate electrode G1 and gate electrode G2 are placed close, the longitudinal direction of the gate electrode G2 is placed along and in the proximity of the longitudinal direction of the gate electrode G1. Furthermore, in the case where the source electrode S1 and source electrode S2 are placed close, the longitudinal direction of the source electrode S2 is placed along and in the proximity of the longitudinal direction of the source electrode S1.

[0198] However, the first semiconductor device, second semiconductor device, third semiconductor device and fourth semiconductor device do not have to be the multi-finger type FETs respectively. For instance, the configurations may be as shown in FIGS. 3 to 5. Even in that case, the same effect as above can be obtained if any of the pairs of the drain electrode D1 and drain electrode D2, gate electrode G1 and gate electrode G2 and source electrode S1 and source electrode S2 is mutually close.

[0199] This embodiment was described by illustrating the double balance mixer. However, the present invention is not limited to the double balance mixer, but includes a circuit apparatus for sharing the source of each FET by using the semiconductor differential circuit of the present invention.

[0200] Furthermore, it is also thinkable to use the bipolar transistors instead of the MOSFETs.

[0201] The circuits illustrated in the above description indicate the operation on the assumption that each semiconductor is a p type. However, needless to say, it is not limited thereto, but the same effect as above can be obtained with an n type.

[0202] The semiconductor differential circuit according to the present invention is capable of miniaturizing the IC chip, and is useful in the oscillation apparatus, amplifying apparatus, switching apparatus, mixer apparatus and so on. 

What is claimed is:
 1. A semiconductor differential circuit comprising: a semiconductor substrate, a first semiconductor device formed on said semiconductor substrate, having a first gate electrode for having one of differential signals conveyed thereto and a first drain electrode for outputting one of the differential signals controlled by said first gate electrode; a second semiconductor device formed on said semiconductor substrate, having a second gate electrode for having the other of said differential signals conveyed thereto and a second drain electrode for outputting the other of the differential signals controlled by said second gate electrode, and wherein: said first drain electrode and said second drain electrode are placed in the proximity so that, at a predetermined frequency, it is equivalent to the one in which said first drain electrode is grounded via a first predetermined resistance, and said second drain electrode is grounded via a resistance of the same resistance value as said first predetermined resistance.
 2. The semiconductor differential circuit according to claim 1, wherein the resistance value of said first predetermined resistance is half the resistance value formed between said first drain electrode and said second drain electrode via said semiconductor substrate, which is determined by space between said first drain electrode and said second drain electrode at said predetermined frequency.
 3. The semiconductor differential circuit according to claim 1, wherein said first semiconductor device and said second semiconductor device are multi-finger type FETs respectively, and are placed so that a longitudinal direction of said second drain electrode is along and in the proximity of the longitudinal direction of said first drain electrode.
 4. The semiconductor differential circuit according to claim 3, wherein: as to said first semiconductor device: said first gate electrode is placed to be adjacent to said first drain electrode along the longitudinal direction of said first drain electrode; and it has a first source electrode placed to be adjacent to said first gate electrode along the longitudinal direction of said first gate electrode, and as to said second semiconductor device: said second gate electrode is placed to be adjacent to said second drain electrode along the longitudinal direction of said second drain electrode; and it has a second source electrode placed to be adjacent to said second gate electrode along the longitudinal direction of said second gate electrode, and a circuit comprising said first semiconductor device and said second semiconductor device is provided as a first unit circuit; n pieces of said first unit circuit are placed to be mutually adjacent; an i+1-th first unit circuit is placed to be adjacent to an i-th (i is between 1 and n−1) first unit circuit; and said n pieces of first drain electrode are mutually connected, said n pieces of second drain electrode are mutually connected, said n pieces of first gate electrode are mutually connected, said n pieces of second gate electrode are mutually connected, and said n pieces of first source electrode and said n pieces of second source electrode are mutually connected.
 5. The semiconductor differential circuit according to claim 3, wherein: a third source electrode is formed on said semiconductor substrate; said first gate electrode is placed to be adjacent to said third source electrode along the longitudinal direction of said third source electrode; said first drain electrode is placed in the proximity of said first gate electrode on the opposite side to said third source electrode along the longitudinal direction of said first gate electrode; said second drain electrode is placed to be adjacent to said first drain electrode on the opposite side to said first gate electrode along the longitudinal direction of said first drain electrode; said second gate electrode is placed to be adjacent to said second drain electrode on the opposite side to said first drain electrode along the longitudinal direction of said second drain electrode, and a circuit comprising said third source electrode, said first gate electrode, said first drain electrode, said second drain electrode and said second gate electrode is provided as a second unit circuit; n pieces of said second unit circuit are placed to be mutually adjacent; said second gate electrode of the i-th (i is between 1 and n−1) second unit circuit is placed to be adjacent to said third source electrode of the i+1-th second unit circuit; and said n pieces of first drain electrode are mutually connected, said n pieces of second drain electrode are mutually connected, said n pieces of first gate electrode are mutually connected, said n pieces of second gate electrode are mutually connected, and said n pieces of third source electrode are mutually connected.
 6. The semiconductor differential circuit according to claim 1, wherein: said first gate electrode is placed to surround said first drain electrode; said second gate electrode is placed to surround said second drain electrode; and a source electrode is placed between said first gate electrode and said second gate electrode.
 7. The semiconductor differential circuit according to claim 6, wherein: there are two pieces each of said first drain electrode and said second drain electrode; a source electrode is placed between one first drain electrode and one second drain electrode; an electrode connected to said source electrode is placed between the other first drain electrode and the other second drain electrode; an electrode connected to said source electrode is placed between one first drain electrode and the other second drain electrode; and an electrode connected to said source electrode is placed between the other first drain electrode and said one second drain electrode.
 8. The semiconductor differential circuit according to claim 1 or 2, wherein: said first gate electrode is placed to be adjacent to said first drain electrode; said second gate electrode is placed to be adjacent to said second drain electrode; and a source electrode is placed to surround said first drain electrode, said second drain electrode, said first gate electrode and said second gate electrode and to be adjacent to said first gate electrode and said second gate electrode.
 9. The semiconductor differential circuit according to claim 8, wherein there are two pieces each of said first drain electrode and said second drain electrode, and one first drain electrode and one second drain electrode are placed to be in proximity, the other first drain electrode and the other second drain electrode are placed to be in proximity, said one first drain electrode and said other second drain electrode are placed to be in proximity, and said other first drain electrode and said one second drain electrode are placed to be in proximity.
 10. A semiconductor differential circuit comprising: a semiconductor substrate, a first semiconductor device, formed on said semiconductor substrate, having a first collector or base for having one of differential signals conveyed thereto; and a second semiconductor device, formed on said semiconductor substrate, having a second collector or base for having the other of said differential signals conveyed thereto, and wherein: said first collector or base and said second collector or base are placed in the proximity so that, at a predetermined frequency, it is equivalent to the one in which said first collector or base is grounded via a second predetermined resistance, and said second collector or base is grounded via a resistance of the same resistance value as said second predetermined resistance.
 11. An oscillation apparatus using the semiconductor differential circuit according to claim 1 or
 10. 12. A switching apparatus using the semiconductor differential circuit according to claim 1 or
 10. 13. An amplifying apparatus using the semiconductor differential circuit according to claim 1 or
 10. 14. A semiconductor differential circuit placement method comprising the steps of: forming on a semiconductor substrate a first semiconductor device having a first drain electrode for having one of differential signals conveyed thereto and a first gate electrode for controlling said one of the signals; forming on said semiconductor substrate a second semiconductor device having a second drain electrode for having the other of said differential signals conveyed thereto and a second gate electrode for having said other signal conveyed thereto formed, and wherein: said first drain electrode and said second drain electrode are placed in the proximity so that, at a predetermined frequency, it is equivalent to the one in which said first drain electrode is grounded via a first predetermined resistance, and said second drain electrode is grounded via a resistance of the same resistance value as said first predetermined resistance.
 15. The semiconductor differential circuit according to claim 1, wherein: it further comprises: a third semiconductor device, formed on said semiconductor substrate, having a second gate electrode for having the other of said differential signals conveyed thereto, and a first drain electrode for outputting one of the differential signals controlled by said second gate electrode; and a fourth semiconductor device, formed on said semiconductor substrate, having a first gate electrode for having one of said differential signals conveyed thereto, and a second drain electrode for outputting the other of the differential signals controlled by said first gate electrode, and the differential signals conveyed to said first gate electrode and said second gate electrode are differential local oscillation signals; said first semiconductor device has a first source electrode for having one of the differential signals to be mixed with said differential local oscillation signals conveyed thereto; said second semiconductor device shares said first source electrode with said first semiconductor device; said third semiconductor device shares said first drain electrode with said first semiconductor device, and has a second source electrode for having the other of the differential signals to be mixed with said differential local oscillation signals conveyed thereto; said fourth semiconductor device shares said second source electrode with said third semiconductor device, and shares said second drain electrode with said second semiconductor device; said differential signals controlled by said second gate electrode are the differential signals having said differential local oscillation signals and said differential signals to be mixed mixed therein; and said first drain electrode and said second drain electrode are placed in the proximity so that, at a frequency of said mixed differential signals, it is equivalent to the one in which said first drain electrode is grounded via a first predetermined resistance, and said second drain electrode is grounded via a resistance of the same resistance value as said first predetermined resistance.
 16. The semiconductor differential circuit according to claim 15, wherein: said first gate electrode and said second gate electrode are placed in the proximity so that, at a frequency of said differential local oscillation signals, it is equivalent to the one in which said first gate electrode is grounded via a third predetermined resistance, and said second gate electrode is grounded via a resistance of the same resistance value as said third predetermined resistance; and said first source electrode and said second source electrode are placed in the proximity so that, at a frequency of the differential signals to be mixed with said differential local oscillation signals, it is equivalent to the one in which said first source electrode is grounded via a fourth predetermined resistance, and said second source electrode is grounded via a resistance of the same resistance value as said fourth predetermined resistance.
 17. The semiconductor differential circuit according to claim 15, wherein the resistance value of said first predetermined resistance is half the resistance value formed between said first drain electrode and said second drain electrode via said semiconductor substrate, which is determined by space between said first drain electrode and said second drain electrode at the frequency of said mixed differential signals.
 18. The semiconductor differential circuit according to claim 16, wherein the resistance value of said third predetermined resistance is half the resistance value formed between said first gate electrode and said second gate electrode via said semiconductor substrate, which is determined by space between said first gate electrode and said second gate electrode at the frequency of said differential local oscillation signals.
 19. The semiconductor differential circuit according to claim 16, wherein the resistance value of said fourth predetermined resistance is half the resistance value formed between said first source electrode and said second source electrode via said semiconductor substrate, which is determined by space between said first source electrode and said second source electrode at the frequency of the differential signals to be mixed.
 20. The semiconductor differential circuit according to claim 15, wherein said first semiconductor device, said second semiconductor device, said third semiconductor device and said fourth semiconductor device are multi-finger type FETs respectively, and are placed so that a longitudinal direction of said second drain electrode is along and in the proximity of the longitudinal direction of said first drain electrode.
 21. The semiconductor differential circuit according to claim 16, wherein said first semiconductor device, said second semiconductor device, said third semiconductor device and said fourth semiconductor device are multi-finger type FETs respectively, and are placed so that a longitudinal direction of said second gate electrode is along and in the proximity of the longitudinal direction of said first gate electrode.
 22. The semiconductor differential circuit according to claim 16, wherein said first semiconductor device, said second semiconductor device, said third semiconductor device and said fourth semiconductor device are multi-finger type FETs respectively, and are placed so that a longitudinal direction of said second source electrode is along and in the proximity of the longitudinal direction of said first source electrode.
 23. The semiconductor differential circuit according to any one of claim 20 to 22, wherein: the first source electrode is formed on said semiconductor substrate; said first gate electrode is placed to be adjacent to said first source electrode along the longitudinal direction of said first source electrode; and said first drain electrode is placed to be adjacent to said first gate electrode on the opposite side to said first source electrode along the longitudinal direction of said first gate electrode; said second gate electrode is placed to be adjacent to said first drain electrode on the opposite side to said first gate electrode along the longitudinal direction of said first drain electrode; said second source electrode is placed to be adjacent to said second gate electrode on the opposite side to said first drain electrode along the longitudinal direction of said second gate electrode; said first gate electrode is placed to be adjacent to said second source electrode on the opposite side to said second gate electrode along the longitudinal direction of said second source electrode; said second drain electrode is placed to be adjacent to said first gate electrode on the opposite side to said second source electrode along the longitudinal direction of said first gate electrode; said second gate electrode is placed to be adjacent to said second drain electrode on the opposite side to said first gate electrode along the longitudinal direction of said second drain electrode, and a circuit having said first source electrode, said second source electrode, said first gate electrode, said second gate electrode, said first drain electrode and said second drain electrode is provided as a third unit circuit; n pieces of said third unit circuit are placed to be mutually adjacent; said second gate electrode of an i-th (i is between 1 and n−1) third unit circuit is placed to be adjacent to said first source electrode of an i+1-th third unit circuit; and said n pieces of first drain electrode are mutually connected, said n pieces of second drain electrode are mutually connected, said n pieces of first gate electrode are mutually connected, said n pieces of second gate electrode are mutually connected, said n pieces of first source electrode are mutually connected, and said n pieces of second source electrode are mutually connected.
 24. A mixer apparatus using the semiconductor differential circuit according to any one of claim 1, 10 and
 15. 25. A circuit apparatus sharing an FET source, using the semiconductor differential circuit according to claim
 1. 